Data storage devices generally operate to store and retrieve data in a fast and efficient manner. A top level controller, such as a programmable processor (CPU), can utilize a hierarchical memory structure to manage data during such transfers with a main memory of the device, such as a semiconductor array of non-volatile memory cells, magnetic media, etc.
Such hierarchical memory structures can include cache, which generally comprises one or more relatively small memory blocks of relatively high speed memory operationally proximate the controller. The cache is generally used to maintain processing efficiencies of the controller as high as possible by minimizing the wait times required to access the relatively slower main memory.
Multi-level caching can be used wherein multiple cache levels (e.g., L1, L2, L3) are successively defined along a pipeline memory structure of the device. If requested data is resident in a selected cache level, the data can be quickly retrieved for use by the controller (a cache hit), thereby eliminating the latency required to access the slower main memory to retrieve the requested data.